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CML Semiconductor Products
CDPD Wireless Modem Data Pump
1.0
* * * *
FX949
D/949/5 March 1996 Advance Information
Features MES Full Duplex Operation Forward Channel Decoding Reverse Channel Encoding Error Detection and Syndrome Output
* * * *
19.2kb/s GMSK Modulation Sleep Timer Included 3.3V and 5V Applications PCMCIA Package Option
1.1
Brief Description
The FX949 is a low power CMOS integrated circuit which performs all of the real-time signal and data format-management functions required for full-duplex operation of a CDPD Mobile End Station. The FX949 interfaces directly with the analogue modulation and demodulation circuits of the radio and the host radio/application processor bus. It accepts application data from the processor, constructs a correct Reverse Channel packet containing this data and converts the packet to GMSK analogue signals for transmission. In receive, Forward Channel GMSK signals from the discriminator are demodulated, the packet disassembled, error checked, and the recovered application data passed to the processor. The FX949 is the cost, size, and power efficient alternative to DSP design solutions in high performance OEM products for the Cellular Digital Packet Data wireless services.
(c) 1996 Consumer Microcircuits Limited
CDPD Wireless Modem Data Pump
FX949
CONTENTS Section Page
1.0 Features.......................................................................................................... 1 1.1 Brief Description............................................................................................ 1 1.2 Block Diagram................................................................................................ 3 1.3 Signal List....................................................................................................... 4 1.4 External Components.................................................................................... 6 1.5 General Description....................................................................................... 9 1.5.1 Software Description ....................................................................... 9 1.6 Application Notes ........................................................................................ 14 1.6.1 General.......................................................................................... 14 1.6.2 Transmitter (reverse channel) ....................................................... 14 1.6.3 Receiver (forward channel) ........................................................... 15 1.6.4 Timer ............................................................................................. 16 1.7 Performance Specification ......................................................................... 18 1.7.1 Electrical Performance .................................................................. 18 1.7.2 Packaging...................................................................................... 23
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1.2
Block Diagram
Figure 1 Block Diagram
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1.3
Signal List
Package L6 Pin No. 8 9 10 11 12 13 14 15 17 D0 D1 D2 D3 D4 D5 D6 D7 VDD
Package L4 Pin No. 2 3 4 5 7 8 9 10 12
Signal Name Type BI BI BI BI BI BI BI BI Power ) ) ) ) ) ) ) )
Description
8-bit bidirectional tristate P interface data lines.
The positive supply rail. Levels and voltages are dependent upon this supply. This pin should be decoupled to VSS by a capacitor. A bias line for the internal circuitry, held at 1/2 VDD. This pin must be decoupled by a capacitor mounted close to the device pins (see Figures 2 and 3). The output of the Rx input amplifier and the input to the Rx filter. The inverting input to the Rx input amplifier. ) ) ) Connections to the Rx level measurement circuitry. A capacitor should be connected from each pin to VSS.
13
18
VBIAS
O/P
14
19
RX SIGNAL FEEDBACK RX SIGNAL DOC 1 DOC 2
O/P
15 16 17
20 21 22
I/P O/P O/P
18 20 26 27
23 24 31 32
TX SIGNAL Vss XTALN CLOCK/XTAL
O/P Power O/P I/P
The inverted Tx signal output from the modem. The negative supply rail (ground). The inverted output of the on-chip oscillator. The input to the on-chip oscillator, for external Xtal circuit or clock. A 'wire-ORable' output for connection to the controlling P's Interrupt Request input. This output has a low impedance pull down to VSS when active and is high impedance when inactive.
32
36
IRQN
O/P
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Package L4 Pin No. 33
Package L6 Pin No. 37
Signal Name CSN Type I/P
Description
34
38
WRN
I/P
Chip Select. An active low logic level input to the modem, used to enable a data read or write operation. Write. An active low logic level input used to control the writing of data into the modem from the controlling P. Read. An active low logic level input used to control the reading of data from the modem into the controlling P. ) ) ) ) ) ) )
35
39
RDN
I/P
38 39 43 44 45 46 47
41 42 1 2 3 4 5
A6 A5 A4 A3 A2 A1 A0
I/P I/P I/P I/P I/P I/P I/P
7 logic level modem register address select inputs.
1, 6, 11, 19, 24, 30, 36, 37, 40, 41, 42, 48 21, 22, 23, 25, 28, 29, 31
6, 7, 16, 28, 30, 40, 43, 44
) ) ) ) ) ) ) ) ) )
No internal connection: leave open circuit.
25, 26, 27, 29, 33, 34, 35
Internally connected: leave open circuit.
Notes:
I/P = O/P = BI =
Input Output Bidirectional
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1.4
External Components
Figure 2 Recommended External Components (L4)
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Figure 3 Recommended External Components (L6)
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Figure 4 Internal Block Diagram
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1.5
General Description
This device performs most of the Medium Access Control (MAC) layer functions of the CDPD specification as well as generation of the baseband signals in the physical layer, all of which are specifically for the Mobile End Station (M-ES). For details of the system requirements and telegram formats, the user is referred to "Cellular Digital Packet Data System Specification", Volumes 1 to 5, currently available from: CDPD Forum Inc. PO Box 809320 Chicago, IL 60686 United States of America
1.5.1
Software Description From the programmer's viewpoint, the FX949 interface consists of a number of registers, addressable from a 7-bit bus with data supplied on a standard 8-bit P bus, as shown in Figure 4.
Read Only Registers
A0 - A6 HEX ADDRES S $00 $01 $02 | | | | $3C $3D $3E $3F $40 $41 $42 $43 $44 $45 $46 $47 $48 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 RDN WRN CSN REGISTER NAME BIT 7 (D7) BIT 6 (D6) BIT 5 (D5) BIT 4 (D4) BIT 3 (D3) BIT 2 (D2) BIT 1 (D1) BIT 0 (D0)
0 0 0
1 1 1
0 0 0
RX DATA 0 RX DATA 1 RX DATA 2 | | | | RX DATA 60 RX DATA 61 RX DATA 62 RX SYN 1 RX SYN 2 RX SYN 3 RX SYN 4 RX SYN 5 RX SYN 6 RX SYN 7 RX SYN 8 RX SYN 9 RX SYN 10
0 0 0
0 0 0
<-------------------- DATA SYMBOL 0 ------------------> <-------------------- DATA SYMBOL 1 ------------------> <-------------------- DATA SYMBOL 2 ------------------> | | | |
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
<------------------ DATA SYMBOL 60 -------------------> <------------------ DATA SYMBOL 61 -------------------> <------------------ DATA SYMBOL 62 -------------------> <-- SYNDROME SYMBOL 1 > <-- SYNDROME SYMBOL 2 > <-- SYNDROME SYMBOL 3 > <-- SYNDROME SYMBOL 4 > <-- SYNDROME SYMBOL 5 > <-- SYNDROME SYMBOL 6 > <-- SYNDROME SYMBOL 7 > <-- SYNDROME SYMBOL 8 > <-- SYNDROME SYMBOL 9 > = [ r (x) / (x + 1) ] --= [ r (x) / (x + 2) ] --= [ r (x) / (x + 3) ] --= [ r (x) / (x + 4) ] --= [ r (x) / (x + 5) ] --= [ r (x) / (x + 6) ] --= [ r (x) / (x + 7) ] --= [ r (x) / (x + 8) ] --= [ r (x) / (x + 9) ] ---
<-- SYNDROME SYMBOL 10 = [ r (x) / (x + 10) ] ->
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$49 $4A $4B $4C $4D $4E $4F $50
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
RX SYN 11 RX SYN 12 RX SYN 13 RX SYN 14 RX SYN 15 RX SYN 16 STATUS IRQ FLAGS
0 0 0 0 0 0 SYNC SYNCF
0 0 0 0 0 0 DEC DECF
<-- SYNDROME SYMBOL 11 = [ r (x) / (x + 11) ] -> <-- SYNDROME SYMBOL 12 = [ r (x) / (x + 12) ] -> <-- SYNDROME SYMBOL 13 = [ r (x) / (x + 13) ] -> <-- SYNDROME SYMBOL 14 = [ r (x) / (x + 14) ] -> <-- SYNDROME SYMBOL 15 = [ r (x) / (x + 15) ] -> <-- SYNDROME SYMBOL 16 = [ r (x) / (x + 16) ] -> IDLE IDLEF
ERROR
0 TIMEF
<---- SYNC ERRORS---> 0 0 0
TXF
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Read Only Register Description RXDATA0 to RXDATA62 Registers (Hex address $00 to $3E) These are read only registers and all 63 registers are each updated with 6-bit symbols every time a valid SYNC occurs. This is indicated by an interrupt (see SYNC, SYNC ERRORS, and SYNC ERROR LIMIT). SYNDROME SYMBOL 1 to 16 (Hex address $3F to $4E) These 16, 6-bit symbols contain the syndrome calculated from the received data (RXDATA 0 to 62). The syndrome is recalculated every time a valid SYNC occurs. An all zero pattern in the 16 syndrome symbols indicates zero errors in the data. STATUS Register (Hex address $4F) This is a read only register that contains the status of the various functions on the device as described below: SYNC (Bit 7) This bit is set to "1" when a forward channel synchronisation word has been received successfully. (See SYNC ERRORS and SYNC ERROR LIMIT). This bit is reset to "0" when the sync word has not been detected for more than 420 bits (i.e. sync lost). This bit indicates the decode status of the Mobile Data Base Station (MDBS) on the forward channel. This bit is set to "1" when the station fails to decode data successfully, and is reset to "0" when the station is successful in decoding data. This bit will only change and be valid if SYNC (Bit 7) is set to "1". This bit indicates the active status of the Mobile Data Base Station (MDBS) on the forward channel. This bit is set to "0" when the station is in an IDLE state, and reset to "1" when the station is in a BUSY state. This bit will only change and be valid if SYNC (Bit 7) is set to "1". The IDLE bit is derived from a majority decision on the five consecutive busy/idle bits, as in the CDPD specification. The first block of data received in the forward channel will not output any data until the sync word has been found. Once this has been found, the most recent (last) idle bit will be output in the STATUS register, and the IDLEF bit will be set to "1" in the IRQ FLAGS register. The next seven idle bits are output as they come in and, so long as the sync word remains correct, successive idle bits are output as they come in. ERROR (Bit 4) This bit indicates if there are errors in RXDATA. This bit is set to "0" if all syndrome symbols (1 - 16) are "0", i.e. no errors in the data. This bit is set to "1" if any syndrome symbol is not "0", i.e. errors are present in the data. This bit is updated every time a valid SYNC occurs. This 3-bit number indicates the number of errors received in the synchronisation word. It is updated whenever the synchronisation word is in error less than or equal to the number specified by the SYNC ERROR LIMIT bits of the CONTROL register. It also implies the synchronisation word has been received successfully and sets the SYNC bit to "1" (See SYNC above).
DEC (Bit 6)
IDLE (Bit 5)
SYNC ERRORS (Bits 2, 1 and 0)
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IRQ FLAGS Register (Hex address $50) This is a read only register that contains flags to indicate the source of an interrupt, as described below: SYNCF (Bit 7) This bit is set to "1" when the device has decoded the sync word on the forward channel. It also is set to "1" if, after detecting sync, it fails to detect it 420 bits later, indicating sync has been lost. The state of sync can be read from the STATUS register. This bit is reset to "0" after a "read" of the IRQ FLAGS register. When this bit is set to "1" an interrupt may be generated, depending on the state of the IRQ MASK register. This bit is set to "1" when the decode status of the Mobile Data Base Station (MDBS) in the forward channel changes state. The decode state can be read from the STATUS register. This bit is reset to "0" after a "read" of the IRQ FLAGS register. When this bit is set to "1" an interrupt may be generated depending on the state of the IRQ MASK register. This bit is set to "1" when the idle status of the Mobile Data Base Station (MDBS) in the forward channel changes state. The idle state can be read from the STATUS register. This bit is reset to "0" after a "read" of the IRQ FLAGS register. When this bit is set to "1" an interrupt may be generated depending on the state of the IRQ MASK register. This bit is used in transmission of data from the 47 symbol "write only" buffer on the reverse channel. This bit is set to "1" when the buffer is empty and new data can be loaded in. It is reset to "0" after a "read" of the IRQ FLAGS register. When this bit is set to "1" an interrupt may be generated depending on the state of the IRQ MASK register. This bit is set to "1" when the timer expires and it is reset after a "read" of the IRQ FLAGS register. When this bit is set to "1" an interrupt may be generated depending on the state of the IRQ MASK register.
DECF (Bit 6)
IDLEF (Bit 5)
TXF (Bit 4)
TIMEF (Bit 3)
Write Only Registers
A0 - A6 HEX ADDRES S $00 $01 $02 | | | | $2C $2D $2E $2F $30 $31 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 RDN WRN CSN REGISTER NAME BIT 7 (D7) BIT 6 (D6) BIT 5 (D5) BIT 4 (D4) BIT 3 (D3) BIT 2 (D2) BIT 1 (D1) BIT 0 (D0)
1 1 1
0 0 0
0 0 0
TX DATA 0 TX DATA 1 TX DATA 2 | | | | TX DATA 44 TX DATA 45 TX DATA 46 TIMER CONTROL IRQ MASK
X X X
X X X
<------------------- DATA SYMBOL 0 -------------------> <------------------- DATA SYMBOL 1 -------------------> <------------------- DATA SYMBOL 2 -------------------> | | | |
X X X
X X X
<------------------- DATA SYMBOL 44 ------------------> <------------------- DATA SYMBOL 45 ------------------> <------------------- DATA SYMBOL 46 ------------------>
<------------------------------- 0 TO 255 SECONDS ----------------------------> ACQ SYNCM RXHOLD DEC M PSRX IDLEM PSTX TXM CI TIMEM <--SYNC ERROR LIMIT---> (SERL) ERR M 0 0
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Write Only Register Description TXDATA0 to TXDATA46 Registers (Hex address $00 to $2E) These 47 registers can be loaded with 6-bit symbols when the TXF bit in the IRQ FLAGS register is "1". On loading the 47th symbol, the device will generate the 16 symbol parity code and begin the transmit sequence. These registers are buffered, therefore after the TXF bit has gone to "1" there are 47 x 6 bit periods minus the time to generate the 16 parity symbols in which to load all registers, i.e. approximately 14 msec. The controlling P has to re-load the buffer with new data within this time otherwise the old data will be sent again. TIMER Register (Hex address $2F) This register sets a timer to expire from 1 to 255 seconds ("0" disables and powersaves it). The time starts from when the register is first set and expires when the programmed time has passed. On expiry, the TIMEF bit is set in the IRQ FLAGS register and an interrupt may occur. The timer is 1-shot and does not restart until it is programmed again. After power up the TIMEF bit should be reset to "0" in order to initialise the timer. CONTROL Register (Hex address $30) This register is used to control the functions of the device as described below: ACQ (Bit 7) This bit controls the way in which the receiver locks onto the phase and amplitude of the incoming signal. When a carrier has been detected, this bit should be set high for at least 16 signal-bit periods, during which time the receiver measures the signal level (Fast Peak Detect) and sets its phase locked loop (PLL) bandwidth wide enough to lock to the received signal in less than 8 zero crossings. When the ACQ bit is returned low, level measurement enters the slower but more accurate Averaging Peak Detect mode; the PLL enters its medium bandwidth for about 30 signal-bit periods, after which time it will continue in its narrow bandwidth mode. When this bit is set to "1" the receiver "bit synchronisation" PLL will lock. It can be used during times when the signal fades, so that when the signal returns the receiver is still very close to good "bit synchronisation". When this bit is set to "0", the device uses its normal PLL acquisition sequence for "bit synchronisation". When ACQ is high, the RXHOLD bit has no effect. When this bit is "1" the receiver is powersaved. When this bit is "0" the receiver is enabled. After power up, this bit should be programmed to "1" in order to initialise the receiver. When this bit is "1" the transmitter is powersaved. When this bit is "0" the transmitter is enabled. Transmission starts as soon as the PSTX bit goes to "0". Before that time, the CI bit and the TXDATA symbols should be set up for the first transmission. Transmission is terminated as soon as the PSTX bit goes to "1". After power up, this bit should be programmed to "1" in order to initialise the transmitter. This bit sets the continuity indicator for transmission. It should be set to "1" when there are more blocks to follow and set to "0" when the last block begins. The first 47 symbol block transmitted after this bit has gone from "0" to "1" is preceded by the "dotting sequence" and the reverse synchronisation.
RXHOLD (Bit 6)
PSRX (Bit 5)
PSTX (Bit 4)
CI (Bit 3)
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SYNC ERROR LIMIT (SERL) (Bits 2, 1 and 0)
This 3-bit number specifies the maximum number of bits that can be in error in the synchronisation word. When the synchronisation word is recognised with less than or equal to this number of errors the SYNCF bit is set to "1" and the actual number of errors is loaded into SYNC ERRORS. The RXDATA is then loaded into the registers for "Data Symbols 0 to 62", the Rx syndrome is updated, and an interrupt may be generated, depending on the state of the IRQ MASK register. If 5, 6 or 7 errors are programmed to be accepted in the SYNC ERROR LIMIT, falsing of the forward channel sync word may occur.
IRQ MASK Register (Hex address $31) These bits prevent interrupts from occurring as detailed below: SYNCM (Bit 7) When this bit is set to "1" the SYNC interrupt will be gated out to the IRQN pin. When this bit is set to "0" the SYNC interrupt will be inhibited. This bit has no effect on the contents of the STATUS register. When this bit is set to "1" the DEC interrupt will be gated out to the IRQN pin. When this bit is set to "0" the DEC interrupt will be inhibited. This bit has no effect on the contents of the STATUS register. When this bit is set to "1" the IDLE interrupt will be gated out to the IRQN pin. When this bit is set to "0" the IDLE interrupt will be inhibited. This bit has no effect on the contents of the STATUS register. When this bit is set to "1" the Tx interrupt will be gated out to the IRQN pin. When this bit is set to "0" the Tx interrupt will be inhibited. This bit has no effect on the contents of the STATUS register. When this bit is set to "1" the TIMER interrupt will be gated out to the IRQN pin. After this bit is set to "0" the TIMER interrupt will be inhibited. This bit has no effect on the contents of the STATUS register. For systems that are required to work error free and where Reed-Solomon error correction is not implemented, this bit provides the means not to interrupt the controlling P if errors are detected. When this bit is set to "1" all the interrupts will work as specified. When this bit is set to "0", the SYNC, DEC and IDLE interrupts will be inhibited even if the on chip Reed-Solomon error detector indicates there are errors in the data, thus not wasting the controlling P's time with interrupts for incorrect data.
DECM (Bit 6)
IDLEM (Bit 5)
TXM (Bit 4)
TIMERM (Bit 3)
ERRM (Bit 2)
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1.6
Application Notes
Further information on Reed-Solomon codes may be found in "Error Control Coding" by S. Lin and D.J. Costello, published by Prentice Hall in 1983. The ISBN number is 0-13-283796-X. The operation of the FX949 can be split into 3 sections: the Transmitter (reverse channel), the Receiver (forward channel) and the Timer. The operational sequence of each is described below, with reference to the internal block diagram, shown in Figure 4. Data and framing transmission structures are shown in Figure 5 for the reverse channel and in Figure 6 for the forward channel.
1.6.1
General (1) After power up, enable or disable the interrupts by using the IRQ MASK register, depending on whether the IRQN signal or direct polling of the IRQ FLAGS register is being used. (2) After power up, program PSRX (Bit 5 of the CONTROL register) to "1" to initialise the Rx circuitry, i.e: reset the interrupts reset SYNCF, DECF, IDLEF in the IRQ FLAGS register reset SYNC, DEC, IDLE, ERROR, SYNC ERRORS in the STATUS register All other Rx registers are not affected and will be in a random state after power up. (3) After power up, program PSTX (Bit 4 of the CONTROL register) to "1" to initialise the Tx circuitry, i.e: set TXF in the IRQ register to "1" to indicate that the Tx buffer is empty set the interrupt IRQN, if enabled, to request Tx data from the controlling P
1.6.2
Transmitter (reverse channel) (1) After power up, a Tx interrupt is generated, if enabled, and TXF (Bit 4 of the IRQ FLAGS register) is set, indicating the output buffer is empty. (2) (3) The transmitter can now be enabled. CI (Bit 3 of the CONTROL register) should be set to "1" when there are more Tx blocks to follow and set to "0" for the last block. If there is only one block to be sent, i.e. the first block is the last block, then the CI bit should be pulsed from "0" to "1" to "0" to ensure that the dotting pattern and block sync are sent and that CI is set to "0" to indicate the presence of the last block, except just after powersave when the dotting sequence and block sync are added automatically. All 47 symbols (0 to 46) are loaded into the TXDATA registers from the controlling P, finishing the load with the 47th symbol. This set of TXDATA registers is double buffered, therefore any previous data can be sent again by re-loading only symbol 46, i.e. loading symbol 46 indicates that data is ready to be sent. The loading of symbol 46 (as above [4]) triggers the generation of a Reed-Solomon 16 symbol parity code, based on symbols 0 to 46 in the input buffer. The transmitter will wait for the output buffer to become empty (if it is the first transmission it may already be empty). When this condition is met, data is transferred to the output buffer. At this point the data and C1 bit for that block have been defined and will not change whilst setting up for the next block to be sent.
(4)
(5)
(6)
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(7)
The data is EXORed with the pseudorandom sequence (PRBS) as it is transmitted. Once this is done, the output buffer will be empty and the TXF flag with interrupt will be generated, looping the control sequence back to the first step. The input buffer can be re-loaded while the transmitter is transmitting. The CI (continuity indicator) bit is automatically inserted every 9 symbols, during transmission. The 38 bit "dotting sequence" and 22 bit block synchronisation word are added if it is the first transmission after Tx powersave or if the CI bit has just previously gone from "0" to "1" indicating the start of a new transmission block. The signal generated has a data rate of 19.2k bits/sec and is filtered by a Gaussian filter with a BT of 0.5 in the transmit section of the GMSK modem.
(8) (9) (10)
(11)
1.6.3
Receiver (forward channel) (1) The SYNC ERROR LIMIT (SERL) (Bits 2, 1 and 0 of the CONTROL register) is set from "0" to "7" as required by the application. (2) (3) The receiver is enabled using PSRX (Bit 5 of the CONTROL register). The receiver is now able to receive 19.2k bits/sec data via the receive section of the GMSK modem, comprising input filter, slicer and bit synchroniser. A continuous stream of data is fed into the receiver input shift register. When the controlling P receives a carrier detect, it can pulse ACQ (Bit 7 of the CONTROL register) in order to quickly acquire bit synchronisation. If carrier detect is not available or, due to powersave requirements, the controlling device remains unpowered, then slower bit synchronisation will be acquired in approximately 32 bits. The receiver input shift register is continually monitored for the 35-bit synchronisation word interleaved with the data. It correlates the number of errors in the synchronisation word with the maximum number allowed (previously programmed into the SYNC ERROR LIMIT bits of the CONTROL register). When it achieves this limit or less, valid data is assumed to be present. The data is EXORed with the pseudorandom sequence (PRBS) and a 16-symbol syndrome is generated. The data and syndrome are then loaded into the Rx output registers, ready for reading by the controlling P. DEC (Bit 6) and IDLE (Bit 5) of the STATUS register are set according to the data received. SYNCF (Bit 7 of the IRQ FLAGS register) is set and an IRQ is generated. SYNC (Bit 7 of the STATUS register) is set to "1". This indicates that a new block of data has successfully been received and is available for reading by the controlling P. With the first block sync received, the device now checks the DEC and IDLE positions in the next block of data and outputs them with interrupts as they are counted in.
(4) (5)
(6)
(7)
(8) (9)
(10)
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(11)
On-chip circuitry predicts when the next block sync will arrive. If it arrives before that time, the circuit is reset and the sequence loops back to step (6). If the time expires, the SYNCF and IRQ signals will be generated and SYNC (Bit 7 of the STATUS register) will be set to "0", indicating that block sync has been lost and DEC, IDLE and RXDATA are no longer valid.
1.6.4
Timer (1) The IRQ FLAGS register is read, to reset TIMEF (Bit 3). (2) The TIMER register is programmed with the time required, from 1 to 255 seconds, starting the time-out. IRQ and TIMEF are set when time expires. This timer can be used to implement the "sleep mode", as described in the CDPD specification.
(3) (4)
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Figure 5 Reverse Channel Transmission Structure
Figure 6 Forward Channel Transmission Structure
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1.7
1.7.1
Performance Specification
Electrical Performance
Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device.
Supply (VDD - VSS) Voltage on any pin (wrt VSS) Current into or out of VDD and VSS pins Current into or out of any other pin Storage Temperature Operating Temperature L4 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating L6 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating
Min. -0.3 -0.3 -30 -20 -40 -40
Max. 7.0 VDD + 0.3 +30 +20 +85 +85
Units V V mA mA C C
550 9
mW mW/C
800 13
mW mW/C
Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Operating Temperature Xtal Frequency Min. 3.0 -40 4.9149 Max. 5.5 +85 4.9155 Units V C MHz
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Operating Characteristics For the following conditions unless otherwise specified: Xtal Frequency = 4.9152MHz, Bit Rate = 19.2k bits/sec, VDD = 3.3V to 5.0V, Tamb = -40C to +85C. Notes DC Parameters IDD (powersaved) IDD (all enabled) IDD (powersaved) IDD (all enabled) (VDD = 5.0V) (VDD = 5.0V) (VDD = 3.0V) (VDD = 3.0V) 1, 10 1, 10 1, 10 1, 10 Min. Typ. 1.3 5.0 0.5 2.0 Max. 2.0 7.0 1.0 3.0 Units mA mA mA mA
AC Parameters Tx Output Tx O/P Impedance (Tx enabled) Tx O/P Impedance (powersaved) Output Signal Level Power up to Tx O/P Stable Rx Input Rx I/P Impedance (at 100Hz) Rx I/P Amp Voltage Gain (I/P = 1mVrms at 100Hz) Input Signal Level Xtal/Clock Input 'High' Pulse Width 'Low' Pulse Width Input Impedance (at 100Hz) Gain (I/P = 1mV rms at 100Hz) P Interface Input Logic "1" Level Input Logic "0" Level Input Leakage Current (Vin = 0 to VDD) Input Capacitance Output Logic "1" Level (lOH = 120A) Output Logic "0" Level (lOL = 360A) 'Off' State Leakage Current (Vout = VDD)
2 2 7 8
300 0.9
1.0 500 1.0 3
2.5 1.1 5
k k Vpk-pk bits
10 9 0.7 500 1.0 1.3
M V/V Vpk-pk
3 3
40 40 10 20
ns ns M dB
4, 5 4, 5 4, 5 4, 5 5 5, 6 6
70%
-5.0
30% +5.0 10.0
90% 10% 10
VDD VDD A pF VDD VDD A
Notes:
Not including any current drawn from the modem pins by external circuitry. Small signal impedance, at VDD = 5.0V and Tamb = 25C. Timing for an external input to the CLOCK/XTAL pin. WRN, RDN, CSN, A0 - A6 pins. D0 - D7 pins. IRQN pin. For 1111000011110000.. bit sequence, at VDD = 5.0V and Tamb = 25C. (output level is proportional to VDD). 8. Measured between setting PSTX to "'0" and TXSIGNAL becoming stable. 9. For optimum performance, measured at RX SIGNAL FEEDBACK pin, for a '...11110000...' bit sequence, at VDD = 5.0V and Tamb = 25C. 10. At Tamb = 25C only.
1. 2. 3. 4. 5. 6. 7.
(c) 1996 Consumer Microcircuits Limited
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FX949
1.7.1
Electrical Performance (continued) Timing Diagrams
Figure 7 P Interface Timings
(c) 1996 Consumer Microcircuits Limited
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FX949
For the following conditions unless otherwise specified: Xtal Frequency = 4.9152MHz, VDD = 3.3V to 5.0V, Tamb = -40C to +85C. Notes Min. Typ. Max. Units
P Interface Timings (ref. Fig. 7)
tACSL tAH tCSH tCSHI tCSRWL tDHR tDHW tDSW tRHCSL tRACL tRARL tRL tRX tWHCSL tWL Address valid to CSN low time Address hold time CSN hold time CSN high time CSN to WRN or RDN low time Read data hold time Write data hold time Write data setup time RDN high to CSN low time (write) Read access time from CSN low Read access time from RDN low RDN low time RDN high to D0 - D7 3-state time WRN high to CSN low time (read) WRN low time 0 200 11 11 200 50 0 10 0 6 0 0 0 90 0 175 145 ns ns ns clock cycles ns ns ns ns ns ns ns ns ns ns ns
Notes:
11. With 30pF max. to VSS on D0 - D7 pins.
(c) 1996 Consumer Microcircuits Limited
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FX949
1.7.1
Electrical Performance (continued)
Note:
This graph does not include the improvement in error rate that is achievable if error correction is included in the user's application software.
Figure 8 Typical Raw Bit Error Rate for Xtal frequency = 4.9152MHz, VDD = 5.0V, Tamb = 25C
(c) 1996 Consumer Microcircuits Limited
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CDPD Wireless Modem Data Pump
FX949
1.7.2
Packaging
Figure 9 TQFP Mechanical Outline: Order as part no. FX949L4
Figure 10 PLCC Mechanical Outline: Order as part no. FX949L6
(c) 1996 Consumer Microcircuits Limited
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D/949/5
CDPD Wireless Modem Data Pump
FX949
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.
CONSUMER MICROCIRCUITS LIMITED
1 WHEATON ROAD WITHAM - ESSEX CM8 3TD - ENGLAND Telephone: Telefax: +44 1376 513833 +44 1376 518247

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